Present circuit design utilizes a plurality of integrated circuits, or chips, which receive a clock signal from a single clock-signal producing device. These chips are usually required to operate at high frequencies. As such, a system which incorporates a plurality of such chips usually requires that each chip operate in synchronism with the clock-signal producing device, which may be located internal or external to the system. It is well known that to correctly detect a data signal from one chip to another, the receiving chip must have at its disposal a clock signal that is closely synchronized with the incoming digital data stream, so as to be able to evaluate logic levels at the most favorable instance. However, not always is the data signal transmitted with an associated clock signal at the same time, in particular, when transmission is performed singularly on a single line.
Generally, it is desirable for all chips using the same clock signal derived from a source chip, to experience a skew of the clock signal which is the same as the skew experienced by the clock signal used by the source chip. However, currently, when a clock signal, derived from a source chip which produces the clock signal, is sent to another chip, or a destination chip(s), the clock signal is first buffered by an output buffer located on the source chip, which drives the clock signal to the destination chip. The output buffer typically adds a delay of a few nanoseconds to the time of propagation for the clock signal to reach the destination chip from the source chip. Typically, the delay is dependent upon the physical load on the buffer, such that, if the clock signal is being distributed to multiple chips, the delay is larger than if the clock signal is distributed to a single chip. The geometric aspects of using a single output buffer to drive the clock signal involves insuring that a low skew of the clock single is fed to all modules on the destination chip.
Generally, data and the clock signal are both created on the same source chip. Thereafter, both the data signal and the clock signal are transmitted to separate output buffers for buffering before being transmitted to the destination chip. Preferably the delay provided by the output buffers is equivalent.
While the data and clock signals are transmitted to a destination chip, which uses the clock signal for, among other functions, data sampling, the original clock signal, before being delayed by the output buffer, is used by the source chip for multiple known purposes, which may include such things as defining a rate at which data is produced.
In addition to the delay provided by the output buffer used by the source chip, the destination chip typically comprises an input buffer that provides further delay to the already delayed clock signal. Once again, the destination chip typically comprises separate input buffers, specifically, one for the data input and one for the clock signal input.
Since the internal clock, as originated, is skewed with respect to the clock signal received by the destination chip, problems may occur in the preparation of data for the next clock cycle. These problems are largely attributed to the delays associated with the output buffer in the source chip and the input buffer in the destination chip. As an example, in a high rate system, if the source chip uses the clock signal for the preparation of data to be transmitted to the destination chip, and the clock signal is delayed by the output buffer before being received by the destination chip, where the clock signal is further delayed by the input buffer, data may change in the source chip before being received by the destination chip, thereby preventing the destination chip from receiving all data from the source chip. Therefore, the data created by the source chip must be held for a period while the clock signal travels to the point of storage. This hold time relates to the delay between the clock input to a register and storage element located in the destination chip.
In order to synchronize the source clock signal with the clock signal received by the destination chip, after being buffered by the output and input buffers, present circuits control their internal clock signals by means of a clock signal generator circuit using a phase locked loop (PLL) circuit. This PLL circuit makes use of a delay line loop (DLL) system that uses a delay line circuit in an oscillator to delay a reference clock signal by one cycle to synchronize with a rising edge of a following clock cycle, thereby synchronizing the clock signal of the source chip to the clock signal received by the destination chip.
While PLLs have been used to regenerate clocks from data, PLLs are presently used to aid system clocking issues. This has occurred because the on-line chip clock frequencies have increased to the point where having to allow for small skews, at the board level, can decrease the overall speed of the system dramatically. The PLL allows an internal clock to be generated that is in phase with an externally delivered clock.
Unfortunately, a PLL consists of a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator, all which add to the circuitry of a chip, and therefore, the cost of manufacturing a chip having a PLL.
Therefore, there is a need in the art for less expensive and more efficient systems and methods for balancing clock distribution between two chips.